Analytical and hands-on Computer Engineering graduate specializing in hardware-software co-design, multi-node sensor networks, and low-latency telemetry architectures. Proven expertise in configuring microcontrollers (ESP32, AVR/Arduino) and managing peripheral communication protocols (SPI, UART, I2C) to bridge edge hardware with wireless network infrastructures. Co-author of peer-reviewed, internationally published technical research at the 2025 IDAP Symposium focusing on autonomous data ingestion and packet parsing via wireless TCP/IP sockets. A proactive troubleshooter with a strong track record of diagnosing physical hardware constraints, performing power-budget audits, and ensuring signal integrity in real-world deployments.
